Appendix · reference

ARM Mali-T860 MP4 (panfrost)

Midgard GPU driven by the in-tree panfrost port

Identity

PartARM Mali-T860 MP4 (Midgard, 4 shader cores)
RoleOpenGL ES 3.1 / Vulkan-class GPU for compositor and 3D clients
Bus / addressMMIO 0xff9a0000 (GPU register bank), behind on-SoC IOMMU and CRU GPU power domain
GPIO / IRQthree GIC SPIs (job, mmu, gpu)
DatasheetARM Midgard architecture overview (closed); register surface is via panfrost UABI headers
Pine64 wikiPinePhone Pro main page
Schematicon-SoC (no external schematic)

Status — ◐ partial

Panfrost attaches, exposes a DRM render node, and Sway uses the GPU rather than falling back to pixman. glxinfo reports Mali-T860 (Panfrost) and glxgears is hardware-rendered. The 2026-05-05 Sway bench, after restoring the patched FreeBSD-platform libdrm, measured vblank_mode=0 glxgears -info at 1339 FPS average and a short glmark2 --size 320x480 -b :duration=1 score of 859. Kernel #175 then reran the same short pass at score 882 and completed the longer 420x760 default glmark2 pass at score 609. That larger run entered warm thermal policy but exited cleanly: no panfrost timeouts, no resets, and active_jobs=0 after glmark2 closed.

Later on 2026-05-05, 59bde6a panfrost: add OPP-aware GPU DVFS , d3b80a7 panfrost: avoid active-job DVFS transitions , 70a9c84 panfrost: quiet DVFS transition logging , and 3bfc1d0 panfrost: avoid max clock for light auto work turned the GPU clock path into an OPP-aware DVFS path. Kernel #172 idles mostly at OPP1 (297 MHz / 825 mV) with occasional OPP0 (200 MHz / 825 mV), keeps transition logs behind dev.panfrost.0.debug_mask=0x40, and ramps to OPP4 (594 MHz / 925 mV) under sustained glxgears load. The controlled Sway/Xwayland runs measured 1468 FPS in performance mode and 1448 FPS in auto mode without panfrost faults, timeouts, or panics. Closing a GL client no longer panics after the per-file MMU/GEM/job lifetime fix in be91afa Refcount Panfrost file lifetime . The 420x760 glmark2 wedge was a reset-path bug: 2b134eb panfrost: wait for GPU reset completion gives reset completion a real wait window, falls back to hard reset, and restores GPU interrupt masks after reset. Heavy / sustained display disruption still triggers a separate drm_modeset_lock wedge in some paths, and the first Firefox bench exposed a newer Panfrost-side hang: firefox’s glxtest left Sway unkillable in panfrost_ioctl_wait_bodma_resv_wait_timeout_rcu. SIGKILL could not reap the Sway process, and sudo reboot stopped sshd but then hung late while the kernel still answered ICMP. The next concrete step is to run mise run debug:gpu:wedge:phone -- <name> before killing clients so the receipt captures whether the current failure is the Panfrost BO wait or the older DRM atomic/modeset path.

Driver

Significant divergence from upstream Linux panfrost lives in job-scheduler and reset-fence handling. The current tree carries four panfrost crash fixes against the drm-subtree baseline: 3378d3d Queue Panfrost reset before scheduler stop , cf2dd90 Fix Panfrost reset fence signaling context , f5184d0 Harden Panfrost reset fence recovery , and be91afa Refcount Panfrost file lifetime . Runtime debug mask, counters, and state-dump sysctls were added in 8accb27 panfrost: runtime debug mask, counters, and state-dump sysctls for the load-test wedge investigation. The OPP/DVFS path is local FreeBSD plumbing over the RK3399 OPP table and regulator framework, not yet upstream-shaped Linux panfrost code.

Open work