Appendix · reference

Rockchip RK3399S (application processor)

Six-core SoC driving the PinePhone Pro: 2x A72 + 4x A53

Identity

PartRockchip RK3399S (voltage-locked variant of RK3399)
RoleApplication processor; 2x Cortex-A72 + 4x Cortex-A53, Mali-T860 MP4, all on-SoC peripherals (CRU, pinctrl, GPIO, I2C/SPI/UART/I2S, USB2/USB3, VOP, DSI, ISP, IOMMU)
Bus / addresson-SoC; per-block MMIO ranges across 0xff000000-0xff9fffff and 0xfe000000-0xfe9fffff
GPIO / IRQ5 banks, 32 pins each (GPIO0-GPIO4); GIC-400 interrupt controller
DatasheetRockchip wiki — RK3399, TRM Part 1
Pine64 wikiPinePhone Pro main page
Schematicsheet 1 (CPU core), sheet 2 (DDR), sheet 3 (clocking)

Status — ● working

All six cores boot from SD via FreeBSD stable/15 arm64 with the Rockchip clock, reset, pinctrl, GPIO, I2C, PWM, SD/MMC, USB, and DRM pieces layered by the mise patch pipeline. Display, GPU, USB networking, native WiFi, Bluetooth A2DP, audio playback, sensors, buttons, and LEDs all work. The S variant differs from the plain RK3399 in that several voltage rails are pre-selected by Rockchip fuse settings rather than software-programmable.

Driver

The S variant boots fine on the standard rk3399.dtsi tree because the differences are voltage-rail constraints, not register-map changes. Our DT pulls in rk3399-pinephone-pro.dts from the Linux device-tree subtree at sys/contrib/device-tree/src/arm64/rockchip/. The big remaining divergence from a clean port is the cluster of write-blocking patches around the CRU, where we forbid writes to PLLs that the early port found capable of crashing the SoC — see bb92c4f cru: allow CPLL/GPLL/NPLL/VPLL, only block CPU PLLs (LPLL/BPLL) and DDR (DPLL) and c985e63 audio: use RT5640 internal PLL from BCLK, restore full CRU PLL block .

Open work