Appendix · reference

Silergy SYR827 + SYR828 (CPU/GPU VDD regulators)

Dynamic voltage regulators for the A72 cluster and Mali GPU rails

Identity

PartSilergy SYR827 (vdd_cpu_b) and SYR828 (vdd_gpu) — fan53555-compatible single-output buck regulators
RoleDynamic per-rail voltage control. SYR827 supplies the A72 big-cluster VDD; SYR828 supplies the Mali-T860 GPU VDD on this board (note: the FreeBSD HARDWARE.md table previously labelled SYR828 as “A53 little cluster” — the upstream PinePhone Pro DTS labels it vdd_gpu).
Bus / addressi2c1 addr 0x40 (SYR827), 0x41 (SYR828)
GPIO / IRQvsel1_pin and vsel2_pin pinmuxed in DTS for VID select; no IRQ used by FreeBSD
DatasheetSYR82x family datasheet (Silergy / community archive)
Pine64 wikiPinePhone Pro hardware
Schematicsheet 9 (CPU / GPU power rails)

Status — ● working

Both regulators come up at boot and hold their U-Boot-configured output voltages. The DTS marks them regulator-always-on and regulator-boot-on and the SoC runs at the resulting fixed operating point — full 6-core SMP and Mali GPU activity work without dropping rail. There is no run-time DVFS in our tree (no FreeBSD driver hooks into these regulators to bump VDD on cpufreq transitions); we are running at a single safe voltage step.

Driver

In Linux, fan53555 registers as a regulator with cpufreq consumers that bump VDD on operating-point transitions. We don’t have any of that wiring — cpufreq runs in HARDWARE.md’s table as “Working” because the cores scale, but at a fixed voltage. Adding a real driver is on the list once any of the runtime power-management work (suspend, DVFS, GPU OPP) lands.

Open work